Senior Manager, ASIC Engineering Uniquify, Inc.
Responsible for developing leading edge System On Chip (SoC) solutions in various technology nodes that include 28nm, 32nm, 40nm. Main responsibilities include, but are not limited to leading and driving the ASIC physical design group in ASIC implementation and verification; execution of various ASIC projects from RTL to GDSII, including synthesis, STA, power analysis, place and route, physical verification, etc; participating in EDA tool selection and management; defining and implementing the ASIC flows and methodologies; project scheduling and planning. Manage a team of 5 to 7 engineers working in close collaboration with other teams that include DFT, Verification, IP, FPGAs.
Master's degree in electrical engineering or relevant/related field plus 3 years experience that must have been gained in ASIC design and methodology experience and have included at least 1 year of management experience. Must have at least one full chip tapeout & a strong background in working with leading-edge process technology (40nm, 32nm, 28nm) and taking multiple designs through the complete netlist to GDS flow is required. Strong communication and management skills are required. Will accept a Bachelor's degree + 5 years of progressive experience in lieu of primary requirements.
||Santa Clara, CA |