Santa Clara Categories:
Senior Physical Design/Chip Integration Engineer SeaMicro
SeaMicro is looking for an experienced Senior Chip Integration Engineer to drive the physical implementation of our next generation super-compute style fabric ASIC. This is an excellent opportunity for high-energy candidates with strong technical leadership skills to take a chip from conception, through execution, to first customer shipment.Responsibilities:
Work with a team of ASIC RTL Designers and provide technical leadership in driving full chip physical design
IP selection and integration: chip I/O, PLLs, high speed PHYs, memories and other
Custom clock design and distribution methodology
Full chip STA constraints
Set up and execution of full chip synthesis and static timing analysis
Ability to manage Signal integrity and I/O verification through part time resources
Work with our backend and manufacturing partner to ensure quality and execution
IP selection, Process technology and Library selection
Chip floor-plan, including I/O placement
Place & route
Thermal and power analysis and planning
Package design
BIST and scan insertion, vector generation
General project management
Qualifications:
10+ years of experience in backend physical design of CPU/SOC ASICs
Must have a strong background in all aspects of ASIC implementation, especially with Synthesis flow, Static Timing Analysis, Floor-planning and I/O ring design
Experience with backend vendor and IP management required
Experience with designing for advanced process nodes
Experience with silicon and system bring up
Excellent communication skills
Candidate will likely have an MS EE with 10+ years of experience
| Location: | 4677 Old Ironsides Drive Suite 310 Santa Clara, CA 95054 United States |
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SeaMicro
All Jobs: at SeaMicro| Web Site: | www.seamicro.com |
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| Headquarters: | 4677 Old Ironsides Drive Suite 310 Santa Clara, CA 95054 United States |
| Industry: | Cleantech / Energy |
