Senior RTL Designer - FPGA RipCode

he successful candidate will be responsible for the FPGA design of both future products and legacy product feature adds. Candidate should have the ability to work from an Architecture Requirements Document and drive the design through implementation. Candidate should have hands-on lab experience as well. Candidate will work with cross functional teams.

Requirements include:

Experience with all aspects of the FPGA design flow (synthesis, place and route, Chipscope, etc)
Self-starter that can work independently
Strong RTL design/coding experience in Verilog
Track record of shipping FPGAs or ASICs in product
Networking background is a must
Experience with a majority of the following XAUI, GigE, S/XGMII, PCIe, DDR2/3, MPEG-2 TS, I2C, SPI
Excellent teamwork. Must work with cross functional teams software, diagnostics, systems.
Excellent written and oral communication skills. Must author Micro-Architecture Specification, as an example
Should have hands on lab experience, strong debug capability
Design for testability and ease of debug
Video background is a plus
Perl, C would be an advantage

MSEE with 5-10 years (or more) of experience.

Location:	1130 East Arapaho Road Suite 435 Richardson, TX 75081 United States