Senior/Staff Design Engineer Kilopass Technology
The ideal candidate will be a member of a next generation advanced NVM design team and have the opportunities to participate in IP generation. The candidate must be a team player with good written and verbal communication skills, and is self-motivated, detail oriented, and able to work with cross-functional teams.
Contribute in all parts of advance memory development flow, starting at design spec.
Standard CMOS-based non-volatile memory circuit design
Lead NVM IP design flow in multiple technologies and foundries
Perform silicon verification, test and debug to analyze the IP on silicon
Post layout extraction & simulation, testing in conjunction with silicon validation.
Working with layout designers.
Skills and Experience Required
5+ years of industry Experience as a memory or non-volatile memory circuit designer
Strong fundamentals of CMOS-based circuit design.
Experience in running circuit simulation tools (FINESIM, HSIM, HSPICE etc.) is required.
Must have prior experience with Cadence circuit design tools (Schematic, Analog Artist, and Layout).
Good knowledge in low power, high speed circuit and signal integrity
Hands-on experience on sense-amplifier, charge pump, high voltage regulator, and bandgap reference design
Experience with statistical design methodology (generating and analyzing Monte-Carlo results) is a plus
Hands-on experience of Si debugging (FIB, micro-probing, post layout RC extraction, etc.) and test equipment (Kalos and MOSAID tester, etc.)
IP Memory compiler design experience is a plus
||3333 Octavius Drive |
Santa Clara, CA 95054