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Senior Verification Engineers Avalent Technologies
Required Skill and Experience:Minimum BSEE/BSCS with 5 years of experience in hardware verification. A strong background in the functional verification of an embedded microprocessor. Previous experience in the instruction-set architecture and micro-architecture of the processor, developing diagnostic tests in assembly language with coverage analysis and bug isolation required.
Responsibilities:
Able to work independently with self motivation to meet aggressive schedule and deadline. Responsible for large block and full chip level / debug, power and clock design in deep sub-micron SoC.
| Location: | 405 River Oaks Parkway San Jose, CA 95134 United States |
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| Full Time |
Avalent Technologies
Investors: Sycamore VenturesAll Jobs: at Avalent Technologies
| Web Site: | www.avalent.com |
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| Headquarters: | 405 River Oaks Parkway San Jose, CA 95134 United States |
| Industry: | Semiconductors |
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