Sr. ASIC Verification Engineer Altierre
Experienced ASIC verification engineer that can take ownership of verification environment, develop new verification IP components in system verilog. Responsibilities include, developing of verification plan, verification IP module specs, writing system
verilog test benches and verification models, and debugging RTL designs. Candidate must enjoy being part of a dynamic start-up environment, that is highly motivated and customer focused to deliver high quality ASIC designs in a timely manner.
BE (EEE, ECE, CSE) 5 years experience
Expert knowledge of System Verilog
Experience writing test verification plans, and executing verification
components development to achieve coverage and schedule identified in
Expertise with Mentor Questa systemVerilog simulation, and Novas Verdi
Must have led the verification, at least 2 complex multi million gate
Excellent communication skills. Organizational skill must include
effective Project tracking and reporting.
||170 Rose Orchard Way |
San Jose, CA 95134
|Employment Type:||Full Time|