Sr. DFT Engineer SandForce, Inc.

Responsibilities:
As a DFT Engineer at SandForce, you'll be responsible for setting up cutting edge DFT methodology and for the implementation and verification. In this position you will be responsible for block level and chip level DFT and helping the design team with all aspects of DFT insertion. These include test mode controllers, IO Bist, Memory Bist and JTAG. In addition you will be responsible for scan insertion and ATPG and post silicon validation.

Minimum Requirements:

- 7+ years of experience in DFT / design
- Strong logic Design, Verilog RTL and verification back ground with experience in STA utilizing industry standard tools
- Must possess a strong knowledge of DFT including scan, BIST, JTAG, Boundary scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing and high speed I/O testing
- Programming in Perl, tcl and c/c++ is a plus


Education:

- BSEE required, MSEE or PhD is preferred.

Location:	Saratoga, CA United States