Sr. R&D Engineer (TIE Compiler) - 440 Tensilica

Tensilica is looking for a highly motivated and talented individual to work on the TIE compiler. TIE (Tensilica Instruction Extension) is a language that allows the designer to customize a processor with new instructions, register files and interfaces, delivering an order of magnitude improvement in application specific performance while maintaining an easy and complete software development environment. The TIE compiler is a proprietary compiler that compiles TIE into verilog HDL as well as libraries for the software tool chain.

RESPONSIBILITIES:


Enhance the TIE compiler to support new state-of-the-art Xtensa architectural features
Define and implement new TIE language constructs with new functionalities
Optimize and improve the TIE compiler on existing TIE language features
Update documentation on new and enhanced TIE language features


REQUIREMENTS:


Excellent interpersonal, communication, and organizational skills
Excellent C programming skills. Experience with C++ is a plus
Experience working with scripting languages such as perl
Experience with compiler optimization techniques
Good knowledge of computer architecture and microarchitecture
Good knowledge of the Verilog hardware description language
Familar with EDA synthesis and verification tools such as DC, ICC, VCS, Conformal
MSEE, MSCS or PhD or equivalent work experience.

Location:	3255-6 Scott Boulevard Santa Clara, CA 95054 United States