Sr. Staff Analog Design Engineer Inphi
MSEE or PHD with minimum of 12+/10+ years experience in deep sub-micron analog/mix-signal circuit design.
High-speed and analog circuit design experience including one or more of the following: PLLs, DLLs, High-speed custom and I/O, SerDes, Clock and Data Recovery, DDRx/GDDRx Receiver or Driver.
Deep sub-micron process design experience at 40nm or 65nm.
A track record of developing high volume commercial products
Working knowledge of industry best practices.
Experience of leading a 2-3 people team is a plus
Strong fundamentals in circuit theory, design, and layout
Creative design ability to solve problems demanding the highest levels of speed and power performance
Experienced in Cadence design flow
Strong communication and presentation skills
Ability to work independently as well as in teams
Ability to work across functions and levels
||Santa Clara, CA |