Sr Staff Signal Integrity Designer eASIC
Job ID: US2011013
Senior Staff Signal Integrity Designer is to oversee both Signal and Power integrity and SerDes architecture effort for world-class highly flexible transceiver solutions for multiple eASIC platforms, supporting over 20 protocols with several customer applications. You will be involved in working the following set of protocols PCIe Gen 3.0/2.0/1.0, Gigabit Ethernet, XAUI, CPRI, SRIO, 10G Base-R, Interlaken, etc.
The successful candidate should have an excellent track record in the following areas:
Signal integrity, channel modeling, and timing recovery
Running and developing communication system simulators
Writing specification for design teams.
Presenting design trade-off analyses and implementation recommendations with custom circuit designers
BSEE or MSEE
Experience in both RTL and gate level verification and debug
5 or more years of hands on experience in design, characterization, debug of high Speed SERDES ranging from 1G to 13Gbps
10 or more years of architecture experience with high-speed communication systems
Experience with signal and Power integrity analysis
Experience with using and developing transceiver modeling, analysis, and characterization tools
Experience with lab equipment for high-speed digital systems
Excellent technical communication through presentations and documentation.
||2585 Augustine Drive |
Santa Clara, CA 95054