Sr. Staff Signal Integrity Engineer Inphi
THIS JOB HAS EXPIRED Job Specification
Staff Signal/Power Integrity Engineer
Inphi Corporation, WLV or SCL
Inphi, founded in 2000, is a fabless provider of high-speed analog semiconductor solutions for the communications and computing markets, providing high signal integrity at leading-edge data speeds that are designed to address bandwidth bottlenecks in networks, minimize latency in computing environments and enable the rollout of next generation communications infrastructure.
Inphi is seeking an experienced Staff Signal/Power Integrity engineer for its fast growing line of products for memory, telecom, datacom, computing and test measurement applications. The successful candidate will join the Inphi team in Westlake Village, CA.
The Signal/Power Integrity engineer will be responsible for system level signal/power integrity modeling, characterization and simulations including PCB, package and silicon ICs. The engineer will independently model and analyze the system signal and power integrity simulation results and provide the innovation suggestions to the silicon design teams to improve signal integrity performance and power in system. The engineer will contribute to I/O specification development of different products and subcomponents. The engineer will provide guideline for silicon package designers, PCB board layout engineers and IC designers. The engineer will debug and solve the silicon related signal and power integrity problems in the system.
Master degree in EE with 5+ years of experience in related area or Ph.D. degree in EE with 2+ years of experience in related area.
Strong fundamentals of transmission lines, EM and microwave theory
Understand the basics of integrated circuits designs
Experience with SERDES characterizations and channel equalizations
Experience with VNA and TDR measurements for channel characterizations
Experience in using 2-D and 3-D EM tools such as HFSS, IE3D, ADS.
Experience in using simulations tools such as Hspice, MATLAB, Spectre or ADS.
Board level layout experience (APD or PADS) is a plus
Independently generate accurate trace, via models and build up the system level simulations in tools such as Cadence, Hspice or MATLAB
Independently analyze the simulation results and propose innovations to improve system performance
Good documentation and presentation
Good system level debugging / troubleshooting
Effective communication and team player
||Santa Clara, CA |
THIS JOB HAS EXPIRED