Develop pre-silicon chip and block level verification test plan, verification environment, behavior model, direct functional test cases, regression test suites, and bus monitors. Debug and isolate verification and design bugs. Analyze functional and code coverage.
Masters in EE or related plus 2 years? experience in job offered/IC verification engineering.
Also requires experience using FPGA for ASIC or SoC verification at module, chip and/or system level; knowledge of DDR2 interface, I2C bus, and industrial standards PCI or USB; Verilog, System Verilog, NC-sim/Modelsim, C++, Perl, and CVS.
Westlake Village, CA 91361