Staff Logic Design Engineer -426 Tensilica

As a member of the Logic Design Team for Xtensa processors, you will be responsible for the micro-architecture development and specification of microprocessor cores, multiprocessor sub-systems and their peripherals.



RESPONSIBILITIES:


Provide technical leadership for development of the next generation micro-architecture
Design and implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other EDA scripts to meet timing, area and power goals
Assist with developing testplans, writing functional diagnostics, debugging failures and analyzing coverage information
Work closely with the Design Verification and EDA teams




REQUIREMENTS:


Excellent logic design and technical leadership skills as demonstrated by successful ASIC or SoC implementations
Knowledge of computer architecture and pipelined designs is required. Experience with processor micro-architecture development, especially in designing a new micro-architecture from ground-up is a must
Excellent knowledge of Verilog and popular EDA simulation & implementation tools
Good experience in scripting languages like Perl, Unix shell or similar languages
Some experience with state-of-the-art verification methodologies (ex RTL assertions, coverage, etc) and assembly language programming required
Excellent written and oral communication skills necessary
Good team player and interpersonal skills
MS (or higher) in EE/Computer Engineering with 10+ years of relevant experience.

Location:	3255-6 Scott Boulevard Santa Clara, CA 95054 United States