Staff/Sr Staff Software Engineer, Synthesis Tabula
THIS JOB HAS EXPIRED As a member of the Synthesis Development Team, participate in the development and support of Tabula?s industry leading synthesis engine for new programmable logic devices.
The successful candidate will:
Work cross-functionally with the field, software development and hardware teams to successfully synthesize customer designs, and to enable timing closure in Tabula?s implementation flow
Diagnose issues in large designs, define approaches to address those issues, and implement software solutions to ensure customers? success
Advance the state-of-the-art in RTL synthesis optimization and functionality through the development of new techniques, both specific to Tabula?s devices and to general purpose synthesis
Demonstrated exceptional commitment to customer success
Strong software-engineering background in C++.
Deep understanding of Verilog and VHDL design and synthesis.
Well-established diagnostic skills finding issues in RTL and synthesis algorithms.
Ability and desire to operate in new code bases addressing issues as required.
Sound insights into software architecture and systems development.
Desire to build quality solutions.
Energy, flexibility, and an aptitude for independent and cross-functional development.
Knowledge of FPGAs and FPGA CAD tools, place&route algorithms.
Digital design and timing modeling of digital circuits
Knowledge of I/O protocols (e.g. PCIe, SRIO) and applications typically targeting FPGAs (e.g. networking, imaging, DSP)
5+ industry or post-grad experience.
MS in CS/CE/EE, Ph.D. preferred.
||3250 Olcott Street |
Santa Clara, CA 95054
THIS JOB HAS EXPIRED