Staff Verification Engineer Link_A_Media Devices
4 to 8 years working experience in SoC verification.
Familiar with digital design flow, including synthesis, timing closure, and formal check.
Experienced in C/C++, Verilog/SystemVerilog, Perl.
Familiar with the latest verification methodologies such as VMM, OVM, and UVM.
Experienced in building BFM and C++ models of various SoC blocks.
Experienced in using code coverage, functional coverage, and assertions.
Knowledge in AHB, SATA, PCIE protocols.
||San Jose, CA |