We are looking for a Staff Verification Engineer who will be responsible for defining the test bench environment, generate verification plans and execute test plans using SystemVerilog for next generation Mixed-Signal products. He/she will also contribute to the verification methodology/flow in a mixed-signal IC design environment. The successful candidate will work closely with a team of chip architects, digital design engineers and analog mixed-signal design engineers.
Define pre-silicon verification/test plan for next generation Mixed-Signal/SOC products.
Execute verification plan using SystemVerilog/Verilog using both direct and random test methodology.
Create and debug test case both in RTL and Gate Level simulation environment.
Define and generate assertions and functional coverage points.
Automate verification environment using Perl and Shell Scripts.
Documentation and tracking verification status using coverage matrix and bug tracking system.
BSEE or MSEE or PHD with minimum 10/8/6+ years of experience in multi-million gates of digital/mixed-signal design verification.
Strong language user in SystemVerilog, Verilog, Perl, Unix Shell.
Experience in RTL and gate level verification and debugging pre and post silicon
Verification experience in 2 of the following areas; SOC with embedded ARM processer; SATA/PCI-E controller verification; DDR2/DDR3 memory controller PC chipset; or North/South Bridge controller
Westlake Village, CA 91361