System Verification Engineer Tensilica
Tensilica is a leading provider of configurable embedded processor technology and DSPs for various markets. It is growing to also offer IP subsystems in application domains such as Baseband and Imaging. As a member of the DSP engineering group you will be responsible for the development and implementation of verification testplans and testbenches for application-domain IP subsystems. You will be working with Tensilica?s IP subsystem development team and Tensilica?s verification teams.
Develop verification testplans for IP subsystems ranging in complexity from single-core subsystems through to multicore/manycore subsystems in application domains such as Baseband and Imaging
Review architectural and microarchitectural specifications of subsystems to develop verification testplans
Implementation of verification testplans, individually and as part of Tensilica?s worldwide engineering team.
Develop and implement unit-level component testbenches for RTL components
Develop and implement complete subsystem-level testbenches.
Develop and improve existing verification regression environments and apply to components and subsystems.
Review results of testplan execution and develop and prepare reports on these results including coverage metrics and other relevant metrics
Devise subsystem verification strategies to ensure optimal coverage.
Work with Tensilica?s IP subsystem development and DSP and subsystem verification teams. Provide guidance to more junior staff on verification.
Excellent working knowledge of Verilog/SystemVerilog and popular EDA simulators and test bench methodologies
Excellent working knowledge of advanced verification methodologies and tools including formal verification, assertion-based methods, UVM/OVM/VMM or equivalents. Complete familiarity with random, directed random, constrained random and directed test approaches as applied to complex subsystems.
Familiar with scripting languages like Perl, Unix or similar languages
Excellent written and oral communication skills
Knowledge of DSPs, instructions sets. processor architecture concepts is desirable
Good knowledge of C/C++ is desirable
BS in EE or CS, MS preferred
5+ years of relevant experience in the verification of ASIC/SoCs and in particular, complex subsystems
Santa Clara , California, United States
||3255-6 Scott Boulevard |
Santa Clara, CA 95054