Verification IP Engineer Jasper Design Automation

Job Description / Responsibilities will include the following:

Acquire new and advanced formal concepts
Test verification IP which may require modeling design in RTL.
Document verification IP to aid customers in applying the IP.
Maintain existing verification IP
Develop new verification IP

Job Requirements:

BS or foreign equivalent in Electrical/Computer Engineering with experience in RTL frontend design, verification and applications.
Ability to understand and solve unfamiliar design problems with incomplete information.
Use of formal tools and an understanding of formal methods a plus.
Strong communication skills

At a minimum, you must have:

Solid grasp of digital design concepts
Basic understanding of ASIC design methodologies
Excellent communication and interpersonal skills of digital design concepts
Working knowledge of the VHDL and Verilog design languages
Formal verification experience desired but not required
Scripting skills desired but not required.

Location:	100 View Street Suite 101 Mountain View, CA 94041 United States