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Primarily responsible for Achronix?s SerDes IP product validation and support that includes Hardware verification and debug of all SerDes modes and configurations Integration of the SerDes IP in the FPGA design tool Customer debug and creation of customer facing9/16/2014 San Jose, CA Save This Job
Engage directly with customers to help resolve technical challenges associated with using the Speedster FPGA products, including but not limited to IP, components and tools. Work with internal engineering teams to communicate feedback and issues, and to drive improvement in9/16/2014 San Jose, CA Save This Job
Validation of external memory interfaces, especially DDR3, at the device and system level. Integration of memory IPs in the FPGA design flow, including development and maintenance of simulation test benches. Development of demo designs. Development of FPGA reference designs to9/16/2014 San Jose, CA Save This Job
Achronix Field Applications Engineers are responsible for customer enablement and FPGA field technical support in North America. Achronix target customers use FPGAs in telecommunication, networking, high performance computing, test and measurement and other high performance9/16/2014 San Jose, CA Save This Job
Achronix Semiconductor is a privately held fabless semiconductor corporation based in Santa Clara, California. We design high-performance, low-power FPGAs using Intel?s 22nm and 14nm 3-D Tri-Gate process technology. Achronix is currently shipping its 22nm HD1000 FPGA, making us8/17/2014 San Jose, CA Save This Job
Position Profile Name: High Speed Ethernet Protocol Validation Staff Engineer/Technical Lead Type of Position: Regular, Exempt Reports to: Product Engineering Director Job Description/Responsibilities Primary Responsibilities: ? Validation of high speed protocol8/17/2014 San Jose, CA Save This Job