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Candidates should have BS/MS/Ph.D. in EE, CS, or related fields. Preferred knowledge/experience in the following areas: Timing Optimization - logic synthesis, physical synthesis, timing/power optimization, incremental timing analysis. Clock Tree synthesis - skew analysis,4/15/2015 Santa Clara, CA Save This Job
Preferred knowledge/experience in the following areas: Design and implement integrated circuits, and support design flows using Electronic Design Automation tools, including formal verification methodology development, physical implementation methodology development for4/15/2015 Santa Clara, CA Save This Job