Avalent Technologies

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Web Site:
Headquarters:405 River Oaks Parkway
San Jose, CA 95134
United States
Industry:Semiconductors
Investors:Sycamore Ventures

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Avalent Technologies Jobs

Senior ASIC Engineer

Avalent Technologies

Required Skill and Experience: MS/Ph.D. in Electrical Engineering with 5 years of ASIC design experience. A strong background in ASIC design process and development, Verilog, Synthesis, place and route, and verification. Previous management experience is

7/9/2014  San Jose, CA  Save This Job

Verification Engineers

Avalent Technologies

Verification Engineers Required Skill and Experience: Minimum BSEE/BSCS with 2 years of experience in hardware verification. The ideal candidate is intelligent, motivated, and team-oriented. Involved in the functional verification of an embedded microprocessor. Should be able to

7/9/2014  San Jose, CA  Save This Job

Senior Verification Engineers

Avalent Technologies

Required Skill and Experience: Minimum BSEE/BSCS with 5 years of experience in hardware verification. A strong background in the functional verification of an embedded microprocessor. Previous experience in the instruction-set architecture and micro-architecture of the

7/9/2014  San Jose, CA  Save This Job

IC Design Engineers

Avalent Technologies

Required Skill and Experience: BSEE/MSEE with minimum 2 years in IC logic or circuit design. Must be well versed in Synopsis tools and Verilog set with working knowledge of microprocessor design. Responsibilities: Responsible for IC logic or circuit design of high performance,

7/9/2014  San Jose, CA  Save This Job

Senior IC Design Engineer

Avalent Technologies

Required Skill and Experience: Resp. for logic & physical design of SoC for embedded, consumer, wireless & telecom applications. Job duties include RTL coding & simulation, Place & Route, Back-end physical design, design/timing verification utilizing Cadence & Synopsys tools.

7/9/2014  San Jose, CA  Save This Job