Lead Design Verification Engineer Netronome
THIS JOB HAS EXPIRED The Netronome Silicon Engineering team in Boxborough, MA is expanding and has unique opportunities for qualified individuals to join us to continue the momentum and market leadership of the award-winning NFP product family of network flow processors. These are used in carrier-grade and enterprise-class communications products that require deep packet inspection, flow analysis, content processing, virtualization and security. Netronome is seeking highly motivated and experienced Design Verification Engineers to join our Silicon Engineering team to play a pivotal role in the creation of our next-generation highest-performance Network Processor SoC.
Responsibilities will span the entire ASIC design verification process, including definition and architecture of state-of-the-art, UVM-based, coverage-driven design verification environments; serving as the verification box leader for a major functional block; overseeing and mentoring the DV efforts of fellow box team members; creating and reviewing verification test plans; code development of new SystemVerilog components from bus functional models to test sequences; to the final closure of complete functional coverage.
The role requires a solid understanding of coverage-driven design verification fundamentals, microprocessor and networking architectures, expertise in SystemVerilog code development, as well as proven debug and bug hunting skills.
The successful candidate will work in a collaborative group of highly experienced design verification engineers where knowledge is shared and mentored in strong team spirit. The candidate will work closely with the system architects and RTL designers in a tight-knit local team effort to ensure we deliver the highest-quality first-pass silicon to our eager customers.
The ideal candidate would have the right combination of technical and interpersonal skills including:
Substantial Experience in coverage-driven design verification, networking protocols, system architecture and hardware design.
A history of successfully creating world-class DV environments that deliver first-pass bug-free hardware.
Expert-level understanding of OOP programming, pseudo-random verification techniques, and functional coverage.
Experience with UVM/OVM SystemVerilog, Python, Verilog and Mercurial is most highly preferred. Similar DV experiences with VMM SystemVerilog, C++, SystemC, Verilator, C, Perl, Clearcase/Perforce may also readily apply. Efficacious Specman eRM experience is viewed as a major plus.
Experience verifying 10G+ Ethernet, Interlaken, PCIe, microprocessors and complex cached memory subsystems is highly favored.
Other desirable traits for select team roles may also include: packet switching SW, assembly/firmware microcoding (IXP, ARM), and post-silicon validation experience.
Excellent problem solving and advanced debugging skills.
Good interpersonal skills, be a quick learner, and ready to contribute to a supportive team culture, wherever the need arises
Be able to quickly comprehend new challenges and plan the necessary tasks to meet overall objectives in a timely manner
Be self-motivated and able to work independently
Possess clear written and verbal communication skills, being able to drive team efforts via written plans, specifications and schedules.
Enthusiasm toward driving and embracing the latest in verification methodologies, techniques and languages in a collaborative group setting is seen as a key value.
BS or MS degree in Electrical/Computer Engineering or equivalent
10+ years of silicon hardware design experience.
||Boston, MA |
THIS JOB HAS EXPIRED