We are looking for a Senior Mixed Signal Design Engineer who will be responsible designing Mixed Signal Circuits and Digital Interfaces for analog components, performing ADC/DAC Design, RTL design, synthesis, timing closure and verification. He/she will also contribute to the design methodology/flow in a digital/mixed-signal IC design environment. The candidate will work closely with the team of chip architects, verification engineers and analog mixed-signal design engineers.
- MAS specification, Mixed Signal Circuit implementation.
- Own pre-layout synthesis and timing closure using Cadence design environment.
- Work with backend engineer on post-layout timing closure.
- Work with verification engineering to debug test cases in RTL and Gate Level simulation environment. Define and generate assertions.
- Post-silicon debug and correlation.
- BSEE/MSEE/PHD with minimum 5/3/0+ years of experience in digital/mixed-signal IC design at 180nm or smaller technology.
- Experience of entire design cycle from micro-architecture specification definition, Mixed Signal Implementation, synthesis and timing closure to post-silicon debug and support in lab environment.
- Strong language user in SystemVerilog, Verilog, Perl, Unix Shell.
- Experience in ADC/DAC and SAR design.
- RTL and gate level verification and debug a+.
- Experience in coverage based/random test environment and assertion generation.
- Experience in Cadence design environment using NC-Verilog, RTL compiler, ETS is a plus.
- Design experience in serial links (SPI, SMBus, I2C, etc)
Westlake Village, CA 91361