Sr Staff Engineer, DFT Design Inphi
THIS JOB HAS EXPIRED Inphi Background
Inphi Corporation, a high-speed analog semiconductor company, is the market leader in data transport and signal integrity solutions from fiber to memory. We address the bandwidth, capacity and power issues faced by cloud computing, mega data center, and 40G/100G network environments. By leveraging our core competencies in advanced analog circuit design, signal integrity, power management, packaging and process technologies, Inphi has taken a leadership role in the markets we serve. Founded in 2001, Inphi went through a successful initial public offering in November 2010 and is publicly traded on NYSE under the symbol ?IPHI.?
Our innovative approaches have resulted in the company?s products being first to market in a number of key areas, including 40G/100G drivers and TiAs, as well as 100G Ethernet CMOS SERDES. We are seeking talented individuals to work on demanding technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity.
Inphi is seeking a DFT design engineer who will be work on all aspects of DFT for future Inphi products. This includes helping define & implementing on-chip DFT test hardware, verification of the test hardware in both RTL & gate level, generation of ATE test patterns, validation of ATE test patterns during device bring up, generation of qualification tests and support of teams during matrix & production yield analysis.
The candidate will work closely with the team of chip architects, digital engineers and analog mixed-signal design engineers, validation engineer, ATE engineer through the entire product development cycle and release to production.
Specific experience & in depth knowledge of the following is required: stuck-at & at-speed compression mode scan, memory BIST testing, boundary scan, JTAG TAP and its use in controlling of DFT circuitry. Experience & knowledge of directed functional testing, particularly those targeted at analog or mixed signal components such as ADCs/DACs/PLLs is preferred as is experience of running higher level functional tests on ATE such as loopback/receive/transmit tests.
BSEE, MSEE or PHD with minimum of 7+ year experience of DFT design and validation for deep sub-micron analog/mix-signal or SoC chip development
Expert of standard DFT design/implementation/validation/production testing of SCAN, JTAG, Boundary Scan, BIST etc.
Knowledge of functional DFT design/implementation/validation/production testing of high link built-in self test, timing accuracy test, eye test, DSP/AFE testing, SOC testing etc.
Analytical problem solving skills
Ability to communicate technical issues across different cross functional teams
Experience of device bring up & support as the product goes into production
A track record of developing high quality commercial products
Working knowledge of industry best practices.
||Santa Clara, CA |
THIS JOB HAS EXPIRED