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Candidate must have 3 to 5 years experience in simulation / verification of complex designs in verilog / system verilog. Experience in gate level timing simulation and DFT related experience is a plus. Qualifications: Thorough understanding of verilog constructs and12/31/2013 Santa Clara, CA Save This Job
Following standard practices, implement and veridy deep sub-micron multi-million gate SoC (System on Chip) ASIC Designs. Working as part of a team and under closer supervision, tasks include but are not limited to synthesis of RTL netlist, developement, design and implementation12/31/2013 Santa Clara, CA Save This Job
Description: We are seeking a sharp and highly motivated person whom our experienced ASIC design team can teach and train into an excellent ASIC design engineer. Candidate will work closely with our industry experienced physical design and/or logical design ASIC team developing12/31/2013 Santa Clara Save This Job